1. Field of the Invention
This invention relates to a semiconductor memory device and a method for the operation thereof, and more specifically to a dual port memory equipped with a memory which is accessible in a random sequence and a data register and a method for the operation thereof.
2. Description of the Related Art
FIG. 8 is a block diagram showing the construction of a conventional dual port memory. The dual port memory is provided with a memory cell array which is accessible in a random sequence and in the form of a matrix and a data register which is accessible in a serial sequence. The dual port memory is employed in, for example, a frame memory for a video means.
Referring to FIG. 8, a memory cell array 1 comprises a plurality of memory cells arranged in 512 rows and 512.times.4 columns. Address signals of A.sub.0 to A.sub.8 are externally supplied to an address buffer 2. A row decoder 3 receives desired address signals from the address buffer 2 to select data, namely, one of the rows in the memory cell array 1. A column decoder 4 accepts desired address signals from the address buffer 2 to choose data, namely, four of the columns in the memory cell array 1. Both data in memory cells which have been selected both by the row decoder 3 and the column decoder 4 are outputted to a data input/output terminal r through a sense amplifier and I/O control circuit 5 and an I/O buffer 6. In addition, 4 bits data of WIO.sub.0 to WIO.sub.3 supplied to the data input/output terminal r are inputted to memory cells selected by the row decoder 3 and the column decoder 4 via the I/O buffer 6 and the sense amplifier and I/O control circuit 5.
On the other hand, a data register 7 is constructed of plural registers arranged for each row. Data are transferred row by row between the data register 7 and the memory cell array 1. An address pointer 8 receives signals outputted from the address buffer 2 and processes the same ready for output. A serial data selector 9 accepts outputs of the address pointer 8 to select 4-bits data for the data register 7. The serial data selector 9 is composed of a shift register which successively selects the 4-bits for the data register 7 or is composed of a decoder which chooses the 4-bits data for the data register 7 in response to the address signals. A serial I/O buffer 10 is operated to transfer serial input/output data of SIO.sub.0 to SIO.sub.3 between the serial data selector 9 and a data input/output terminal s.
A timing generator 11 externally accepts a row address strobe signal RAS, a column address strobe signal CAS, a write per bit signal WB and/or write enable signal WE, a data transfer signal DT and/or output enable signal OE, a serial control signal SC a serial enable signal SE so as to produce various timing signals for controlling the operation of each device.
FIG. 9 is a circuit diagram illustrating the construction of a principal part of a memory cell array included in a dual port memory. To explain a conventional dual port memory as shown in FIG. 8 and to simplify explanation of succeeding embodiments, FIG. 9 includes a specific circuit of register DR and a specific structure of transfer gate 12 for connecting the register DR to bit lines. However, such specific circuit of register DR and specific structure of transfer gate 12 for connecting the register DR to bit lines are a part of the present invention.
The memory cell array 1 is provided with a plurality of bit line pairs, namely, paired bit lines BL and BL. A plurality of word lines and two dummy word lines are arranged to extend across these paired bit lines BL and BL. The word lines of X.sub.0 to X.sub.3 and dummy word lines of DX.sub.0 and DX.sub.1 are shown in FIG. 9. Each memory cell MC is provided at an intersection of each word line and each bit line BL or BL. In addition, dummy cells DC are provided at an intersection of the dummy word line DX.sub.0 and the bit line BL and at an intersection of the dummy word line DX.sub.1 and the bit line BL. The plural word lines are electrically connected to the row decoder 3.
Also connected to each of the paired bit lines BL and BL is a sense amplifier SA composed of P-channel MOS transistors Q.sub.1 and Q.sub.2 and N-channel MOS transistors Q.sub.3 and Q.sub.4. A sense amplifier unit 50 is constructed of plural sense amplifiers SA. Each of the paired bit lines BL and BL is connected to a pair of data input/output lines DIO and DIO through N-channel MOS transistors Q.sub.5 and Q.sub.6. A column selection signal is applied to gates of the transistors Q.sub.5 and Q.sub.6 from the column decoder 4. An I/O control circuit 60 is constructed of the plural transistors Q.sub.5 and Q.sub.6. On the other hand, each of precharge circuits PR composed of N-channels MOS transistors Q7 and Q8 is connected to the respective paired bit lines BL and BL. The plural pre-charge circuits PR constitutes a pre-charge circuit unit 70.
Connected to each bit line BL via respective N-channel MOS transistors Q.sub.9 is a register DR composed of N-channel MOS transistors Q.sub.10, Q.sub.11 and Q.sub.12 and inverters G.sub.1 and G.sub.2. A transfer gate 12 is constructed of the plural transistors Q.sub.9. The plural registers DR set up a data register 7. Data lines DL and DL of each of the registers DR are connected to a pair of serial input/output lines SIO and SIO through the transistors Q.sub.11 and Q.sub.12. A selection signal is supplied to common gates of the transistors Q.sub.11 and Q.sub.12 of the respective registers DR from each of selector circuits SL. The plural selector circuits SL constitute a serial data selector 9.
A description will next be made on the operation of a dual port memory shown in FIGS. 8 and 9 with reference to timing charts illustrated in FIGS. 10 and 11.
FIG. 10 is a timing chart for describing a read transfer in the dual port memory. The read transfer means that data read out from each memory cell MC is transferred to the data register 7.
Referring to FIG. 10, the paired bit lines BL and BL have been precharged up to a given precharge potential V.sub.BL at a time t.sub.0 by the precharge circuit unit 70. This potential V.sub.BL is equal to, for example, one-half the power-supply potential V.sub.cc, namely, a potential of 1/2 V.sub.cc. When an equalizing signal EQ is next rendered "L" level (low level) at a time t.sub.1, the paired bit lines BL and BL reach a floating state. At a time t.sub.2, a potential of one of the plural word lines is raised up by the row decoder 3. A potential of the word line X.sub.0 is caused to rise up to "H" level (high level) by way of example. Consequently, data in each of the memory cells MC, which is connected to the word line X.sub.0, are read out to its corresponding bit line BL. A capacitance of each bit line is established at values on the order of usually 10 to 20 times the capacitance of each memory cell. Therefore, a slight potential difference on the order of 100 mV occurs between the paired bit lines BL and BL. At the same time, a dummy cell read-out signal RDO changes from "H" level to "L" level. The dummy cell read-out signal RDO varies in phase opposite to the potential of the word line X.sub.0 with a view toward cancelling noises caused by a capacities coupling of the bit lines at the time of change of the potential of the word line X.sub.0 to "H" level.
Sense amplifier activation signals SP and SN, which are inputted to the sense amplifier unit 50, are gradually changed to "H" level and "L" level at a time t.sub.3 respectively. Thus, a slight potential difference produced between the bit line pairs BL and BL is detected by the sense amplifier SA. At a time t.sub.4, either one of the paired bit lines BL and BL is potentially rendered "H" level completely, while the potential of the other thereof is fully rendered "L" level. The detection of data which have been read out from each memory cell MC is thus terminated.
Although the reading of the data in each memory cell MC is completed at this time, data on each bit line are transmitted to each data register 7 via the transfer gate 12 during a read transfer cycle. A register transfer signal RT is caused to change to "L" level at a time t.sub.5. As a consequence, the data line DL is electrically disconnected from the inverter G.sub.1 in each register DR. At the same time, the data transfer signal DT is caused to change to "H" level. Consequently, the data at each bit line BL is transferred to each data line DL without competing with the data of each register DR. At a time t.sub.6, the data transfer signal DT is then rendered "L" level while the register transfer signal RT is rendered "H" level, whereby an electrical disconnection between the individual bit lines and each data line is established to return each register DR to a stable state.
At a time t.sub.7, a potential at the word line X.sub.0 is rendered "L" level while the dummy cell read-out signal RDO is set to "H" level. As a consequence, a sequential read-out operation is completed and the data which have been read out are stored again in each memory cell MC. When the equalizing signal EQ reaches "H" level at a time t.sub.8, each of the bit line pairs BL and BL is precharged again to be the precharge potential V.sub.BL.
FIG. 11 is a timing chart for describing a write transfer in the dual port memory. The write transfer is concerned with a transfer of data in the data register 7 to each bit line BL contrary to the read transfer.
The capacity of each bit line BL is greater than for each register DR as much as 5 to 10 times. It is therefore difficult to transfer data from each register DR to each of the bit lines BL after operation of the respective sense amplifiers. Upon performance of the write transfer, the data transfer signal DT is usually rendered "H" level before operation of each sense amplifier SA. Consequently, a slight potential difference is produced at each bit line BL by data stored in each register DR and the respective sense amplifiers SA are thereafter activated.
Referring to FIG. 11, each of the bit line pairs BL and BL is precharged to be a precharge potential V.sub.BL (1/2.multidot.V.sub.cc electric potential) at a time t.sub.0. An equalizing signal EQ is next rendered "L" level at a time t.sub.1. Thus, the paired bit lines BL and BL reach a floating state. When the electric potential at the word line X.sub.0 and the dummy cell read-out signal RDO are caused to change at a time t.sub.2, data stored in each memory cell MC are read out to each bit line BL in the same manner as in the read transfer. As a result, a slight potential difference produces between the paired bit lines BL and BL. However, in the write transfer unlike the read transfer, a data transfer signal DT is rendered "H" level and a register transfer signal RT is kept "H" level simultaneously. Consequently, data of each of the registers DR through the data line DL are transferred to each bit line BL via each transistor Q.sub.9 of the transfer gate 12. An electric charge feeding capacity through the data line DL is greater than that through each bit line BL. As a result, a slight potential difference is produced between the paired bit lines BL and BL by the data of each register DR.
Sense amplifier activation signals SP and SN are caused to change at a time t.sub.3, so that each sense amplifier SA is activated. As a consequence, the slight potential difference between the bit line pairs BL and BL is amplified. At a time t.sub.4, one of the paired bit lines BL and BL is potentially rendered "H" level completely while the voltage of the other thereof is completely rendered "L" level, thereby leading to completion of the data detection.
The write transfer is caused to return to an initial state at times t.sub.5 and t.sub.6 in the same manner as in the read transfer.
On the other hand, in a conventional dynamic RAM (which is referred to as Random Access Memory), charging and discharging operations are carried out for each bit line by sense amplifiers upon reading out of data from each memory cell. An electric power consumed by the charge and discharge for each bit line is as much as 80% to 90% of the power consumed in the dynamic RAM. Accordingly, the power consumption can be reduced to substantially half by dividing a single unit of a memory cell array and a sense amplifier unit into two and then separately operating them.
A dual port memory which performs divisionally two-block operations (namely, 1/2 division operation) may be considered, for example, the construction shown in FIG. 12. In order to facilitate its description, a precharge circuit unit, a data selector and an I/O control circuit are omitted from the construction in FIG. 12. In addition, wirings to be connected between adjacent blocks are also omitted therefrom.
The dual port memory illustrated in FIG. 12 is provided with a block A comprising a memory cell array 1a, a row decoder 3a, a column decoder 4a, a sense amplifier unit 50a, a transfer gate 12a and a data register 70a and a block B including a memory cell array 1b, a row decoder 3b, a column decoder 4b, a sense amplifier unit 50b, a transfer gate 12b and a data register 70b. Either one of the blocks A and B is operated for each read-out cycle. Likewise, either one of the blocks A and B is also activated even during the read transfer cycle and write transfer cycle.
Incidentally, data in each memory cell are read out to each bit line by rendering a potential at any one of word lines "H" level during the data read-out cycle and the voltage at each bit line is amplified to be set to "H" level or "L" level by the operation of each sense amplifier. Thus, in the memory cell array in an inactive state, the row decoders are also provided separately since it is necessary to set a selection signal for each word line to "L" level state.
In the dual port memory shown in FIG. 12, data can bi-directionally be transferred between the memory cell array and the data register in internal units of the blocks A and B in accordance with the read and write transfers. It is, however, not possible transmit or receive the data between the two blocks A and B. For instance, after data stored in the memory cell array 1b within the block B have been read-transferred to the data register 70b, the data cannot be write-transferred to the memory cell array 1a in the block A.